In another show of might, IBM has unveiled the world’s first 5nm chip in collaboration with Samsung and GlobalFoundries. Of course, a new chip means better performance, better power management and increased density using smaller transistors. The chip by IBM is one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.
In terms of chip designs, the number of nanometers (nm) is a major deciding factor. GAAFETs, which are the next evolution of tri-gate finFETs, are used in chips of designs and sizes below 22nm. However, they only go as far low as 7nm then become unusable. However, when combined with EUV technology, GAAFETs can go as far below as 3nm. Given that the 5nm has just been unveiled, no one knows what goes on below the 3nm mark.
In the design and manufacture of transistors, the focus was on reducing the size while increasing the power on a two-dimensional plane. However, this design had its limitations given that a size is reached when the switching becomes too slow, leakage becomes high, and reliability becomes an issue. Also, with size, the number of atoms available to ship the electrons across the chip are incredibly reduced to an extent that very few electrons can pass across it.
The use of FinFETs solves this issue since it adds a fin to create a three-dimensional model with a higher surface area for the transmitting of electrons. The reduction in chip size has, however, seen to the further thinning out of the chips making the third dimension irrelevant. To remedy this issue, the use of GAAFETs technology has seen to the adoption of newer models of manufacturing chips such as one employed by IBM and its partners.
With the new chip, IBM has created a GAAFET model that allows for reliability, better performance, and can even be further scaled down to fit into smaller spaces. While the chip can be trimmed down further to a smaller size, IBM chose in the 5nm size since it’s the most optimal size for the best performance.